Digital Logic Gate ICs with Symbols and Truth Tables


The basic logic gates are the building blocks of more complex logic circuits. These logic gates perform the basic Boolean functions, such as AND (IC 7408), OR (IC 7432), NAND (IC 7400), NOR (IC 7402), Inversion (IC 7404), Exclusive-OR (IC 7486), Exclusive-NOR. Fig. above shows the circuit symbol, Boolean function, and truth. It is seen from the Fig that each gate has one or two binary inputs, A and B, and one binary output, C. The small circle on the output of the circuit symbols designates the logic complement. The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. A gate can be extended to have multiple inputs if the binary operation it represents is commutative and associative.

These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC gates are classified not only by their logic operation, but also the specific logic-circuit family to which they belong. Each logic family has its own basic electronic circuit upon which more complex digital circuits and functions are developed. The following logic families are the most frequently used.

TTL     Transistor-transistor logic

ECL    Emitter-coupled logic

MOS    Metal-oxide semiconductor

CMOS    Complementary metal-oxide semiconductor

TTL and ECL are based upon bipolar transistors. TTL has a well established popularity among logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS, are based on field effect transistors. They are widely used in large scale integrated circuits because of their high component density and relatively low power consumption. CMOS logic consumes far less power than MOS logic. There are various commercial integrated circuit chips available. TTL ICs are usually distinguished by numerical designation as the 5400 and 7400 series.

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8 thoughts on “Digital Logic Gate ICs with Symbols and Truth Tables

  1. The equations beside the NAND and NOR gates are wrong, and would not produce the truth tables next to them (which IS correct). i.e., a NAND gate is not ~A × ~B, else its output would only be 1 when both A and B are 0. It is in fact ~(A×B). It’s a small difference, but a significant one.

    Likewise, the NOR gate is ~(A+B) , not ~A + ~B. THAT equation would only result in an output of 0 if BOTH inputs were 1, as a NOT of either input being 0 would be a 1. Interestingly enough, the equation next to the NAND would produce the truth table next to the NOR and vice versa.

    1. Thank you for taking the time to point it out. This was a very old post and apparently I never checked what I posted. I have fixed it now.

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